Abstract:

The Tutorial provides an overview of advanced packaging technologies, emphasizing their significance in integrating diverse functionalities within a single device. It begins with an exploration of the essential roles of packaging, which serves as a connection and protective barrier to the external environment, while also addressing spatial requirements for interconnections. Further focus is package scaling, highlighting the need for increased input/output (I/O) counts, reduced interconnect sizes, and the advantages of novel interconnect technologies and 3D packaging.

A brief technological view examines bonding techniques starting with the evolution of wire bonding, micro bumps for flip chip, and hybrid bonding. Emphasis is given on process interdependencies such as thermal management and planarity. Finally, the presentation outlines the myriad options enabled by advanced packaging technologies, such as the ability to integrate multiple functions into one package, leverage different technologies for optimal performance, utilize smaller chiplets for enhanced yield, and combine novel computing methods like quantum computing with established technologies.

Abstract:

In the ever-evolving technology landscape, the advent of denser technologies has become a catalyst for unprecedented

innovation. Technology scaling enable higher compute density, memory density/bandwidth and hence is a key factor towards scalable

system architecture design. In the more than Moore era, system-technology co-optimization (STCO) is a promising paradigm for

leveraging the synergy between emerging technology and application-driven architectures to achieve higher efficiency and performance

at cost parity. As artificial Intelligence (AI) and Machine Learning (ML), continue to advance and become more integrated into various

industries, there is a growing need for joint optimization across the stack – workloads-architecture-design and technology. In this talk,

we will discuss scaling bottlenecks in four system domains – Mobile; Cloud CPU servers; Datacenter GPUs; Edge Inference accelerators

and the role of emerging technology to mitigate these bottlenecks. 3D Technology offers great opportunities to unlock CMOS scaling –

new device architectures, BEOL boosters, backside technology, functional partitioning and heterogeneous integration, all of which will

play a key role in next generation system architectures. Through system disaggregation, technology specialization and deep scaled

assembly methods, the CMOS2.0 era will be instrumental in the future of dimensional scaling.

Abstract:

Phase locked loops (PLLs) are among the most critical blocks in wireless and wireline applications, and are also used to generate low-jitter clocks for digital processing applications. This tutorial starts with the basics of classic analog PLLs and then moves on to recent architectural innovations that have reduced the RMS integrated jitter of multi-GHz PLLs in modern CMOS technologies to less than 100 fs. 

Abstract:

GlobalFoundries 22FDX is a fully depleted silicon on insulator (FDSOI) technology. 22FDX FET devices realize

ultra-thin silicon channel structures in conjunction with thin buried oxide. The well (i.e., body) below the buried

oxide is electrically isolated from the channel and can be used to tune the effective threshold voltage of the FET

devices by applying body bias voltages. 22FDX realizes two distinct well architectures; flip-well architecture in

support of Forward Body Biasing, and conventional well architecture in support of Reverse Body Biasing.

GlobalFoundries has collaborated with IP partners in developing the industry’s first complete ecosystem to

enable the application of body biasing for customer SoC products. Specifically, IP solutions for Adaptive Body

Biasing are able to reduce the impact of process, voltage, and temperature variation at digital circuit behavior

and thus to further improve the power, performance, and area (PPA) metrics of digital SoC designs. This tutorial

outlines the development of Adaptive Body Bias solutions, based on specific characteristics of 22FDX FET

devices, its design platform enablement covering foundational IP characterization, SoC sign-off methodology,

and PPA optimization strategies. The tutorial concludes with PPA optimization examples of SoC cores.

Abstract:

As the Internet of Things and AI continue to expand, the growing flow of data calls for more energy-efficient computing systems. In this landscape, in/near-memory computing (I/NMC) —where computations occur directly in or near memory— shows great promise. Moreover, with AI’s growing need for vast data processing, the use of non-volatile memories for both storage and computation is becoming crucial. 

This tutorial explores recent advances in resistive memory-based I/NMC technology, focusing on innovative circuits and experimental findings that boost performance while lowering power consumption, paving the way for sustainable edge computing systems.

Abstract:

The automotive industry has been rapidly evolving in recent years, driven by technological advancements that make our cars clean, safe and smart. The use of LED lighting in vehicles has emerged as a key innovation with widespread adoption, driving further innovation in future mobility. Automotive LED lighting systems offer improved safety, enhanced design capabilities, and increased energy efficiency, from exterior to interior lighting. The convergence of LEDs and connectivity is driving a new wave of innovation in the lighting world, and the automotive industry is at the forefront of this change.

In this tutorial, we'll explore the latest trends, technologies, and solutions that are shaping the future of automotive lighting innovation, with a focus on LED driver development and design challenges.