As the CEO of Quobly, a France-based quantum startup founded in 2022, Dr. Maud Vinet is at the forefront of efforts to bring an operable quantum processor to the market rapidly.
Previously, Maud Vinet led the quantum computing program at the world-renowned NRO - the CEA Leti. For 20 years, she ran technology transfer and development for the semiconductor industry. From 2013 to 2019, she managed the Advanced CMOS activities. From 2009 to 2013, she spent 4 years in Albany (NY, US) to develop Fully Depleted SOI within IBM Alliance together with STMicroelectronics.
Maud Vinet has authored or co-authored about 400 papers, she owns more than 70 patents related to nanotechnology and her Google h-index is 57.
Title:
Make qubits like we made transistors: let’s enable large scale quantum computers thanks to silicon
Abstract:
Quantum computing demands major scientific and technological breakthroughs to become practical. Recent advancements in quantum hardware, including superconducting qubits, trapped ions or neutral atoms, photons, and silicon spin qubits have significantly not only improved quantum figures of merit but also paved the way toward actual computation. Google's demonstration of quantum supremacy with superconducting qubits gave a head start in 2019. Recently quantum error correction with logical qubit and operations demonstration has made a leap for reliable and useful quantum computation. As research continues to move the field toward practical applications, the question of scalability becomes pregnant. Si-based qubits are considered the most promising experimental system for scaling quantum computing. We have demonstrated that FDSOI CMOS technology can be turned into a platform to co-integrate hole and electron spin qubits with cryo-electronics making it a prime contender for large scale quantum computers. We will review the latest results and share perspectives on the path to million qubits.
Jan Hoentschel works at GLOBALFOUNDRIES as a Director of the feature-rich CMOS device technology development and is responsible for CMOS devices across multiple technologies. Previously he managed the 22FDX platform development team and the customer engineering team in Fab1. He also led the Low-Power device team and was responsible for various CMOS Device technology development from 90nm down to 22nm FDSOI. Previously, he was working with Advanced Micro Devices (AMD). He is also an Honorary Professor at the University of Applied Science Dresden and an executive member of IEEE IEDM and EDS Manufacturing Committee. Jan has over 20 years' experience in the semiconductor industry, and he is an author and co-author of more than 70 technical papers and 160 patents. He holds a Diploma from the University of Applied Science Dresden and TU Dresden, a Ph.D. in electrical engineering from TU Dresden and an MBA from the University of Applied Science Bielefeld.
Title:
Value Added CMOS Technologies for AI Enriched Products and Applications
Abstract:
The semiconductor industry is a hub of innovation, driving advancements in AI, HPC, 5G/6G, autonomous driving, and IoT. While technology scaling and advanced packaging enhances chip efficiency and performance, propelling Artificial Intelligence IC systems forward special segments like RF, non-volatile memory, power management, CMOS image sensors, and Si photonics expand device innovations to the edge to inference with the “real world” and advance a smart and versatile user experience. These segments are essential to enrich mobility, audio and video demands, communications, automotive and industrial solutions as well as security in a holistic systems using AI “on”- or “off”-chip. Diversity and complexity increase as CMOS technologies enable electronic systems to scale and so-called “smart” or “intelligent” systems are built and communicate vastly at the edge where lowest power is essential since its limitation. The paper explores the latest trends in AI at the edge solutions based on CMOS technologies as well as value added technologies that enable AI enriched products and technologies including their impact on complex CMOS device integration.
Dr Julien Ryckaert received the M.Sc. Degree in electrical engineering from University of Brussels (ULB) in 2000 and the PhD degree from Vrije Universiteit Brussel (VUB) in 2007. He joined imec as a mixed-signal designer in 2000.
In 2010, he joined the process technology division in charge of design enablement for 3DIC technology. Since 2013, he is in charge of imec’s design- technology co-optimization (DTCO) platform for advanced CMOS technology nodes.
In 2018, he became program director focusing on scaling beyond the 3nm technology node as well as the 3D scaling extensions of CMOS.
Since 2021, he is Vice President Logic in-charged of compute scaling.
Title:
CMOS 2.0: a compute system scaling roadmap towards 2050
Abstract:
While entering the nanosheet era, the semiconductor industry realizes that we’re not on a smooth scaling curve for scaling CMOS. Design-Technology Co-Optimization (DTCO) has been instrumental in leveraging the full capabilities of scaled devices since the early finFET days. Moving forward, many disruptions are expected in CMOS platforms to provide scaled competitive nodes. New device architectures, BEOL scaling boosters, backside technology, 3D partitioning, and heterogeneous integration will all become instrumental in providing a future for the scaling roadmap. This trajectory will bring us deep into the CMOS 2.0 era. In this new approach to scaling, compute architectures and technologies will be more entangled than ever. Through system disaggregation, technology specialization and deep scaled assembly methods, new compute architectures are expected to emerge. This will be a rich innovation era at many layers of the technology stack that will require a holistic approach.
Dr. Stefano Fabris is President of the CHIP4POWER consortium, leading the Pilot Line on Wide Bandgap Semiconductors funded by the European Chips Act. Since September 2023, he has serves as the Director of the Department of Physical Sciences and Technologies of Matter at the National Research Council of Italy (CNR), where he also drives technology transfer and collaborations between academia and industry.
Title:
Powering the Digital & Green Twin Transition: The Role of Wide Bandgap Semiconductors in Future Electronics
Abstract:
The ongoing digital and green twin transition is reshaping industries and transportation through electrification, increased energy efficiency, and enhanced connectivity. As power demand surges and renewable energy sources transform the grid, the semiconductor industry stands at a critical juncture, where innovation in power electronics is imperative. Wide bandgap (WBG) semiconductors—such as silicon carbide (SiC) and gallium nitride (GaN)—offer unprecedented advantages in high-power and high-frequency applications, enabling superior efficiency, higher voltage operation, and compact designs.
This keynote will explore the technological advancements in WBG materials, the strategic role of the European semiconductor ecosystem in global competition, and the need for an integrated pilot line to accelerate innovation from lab to fab. We will discuss challenges such as cost reduction, process optimization, and the integration of ultra-wide bandgap (UWBG) materials like Ga₂O₃ and diamond. Additionally, we will highlight how WBG power electronics can drive sustainable solutions across automotive, industrial, and telecommunication sectors while reinforcing Europe’s strategic autonomy in semiconductor technologies.
By addressing the key enablers of next-generation power electronics, this keynote will provide a roadmap for leveraging WBG innovations to meet the energy efficiency demands of a rapidly evolving digital and electrified world.